Thick Silicon Epitaxy Part 1: "Marker washout”
For power device manufacturers, thick silicon epitaxy processes are employed to improve device breakdown voltages and performance. These single crystal epitaxy layers are typically in the 5-30um range and utilize the crystal orientation of the bulk silicon substrate to define their crystal orientation e.g. , .
Depending on the crystal orientation, growth rate, gas flow, gas mixture composition, temperature and pressure, alignment marks suffer varying degrees of deformation. Typically, the markers will lose edge definition, CD control, and step height, often referred to as “washout”. In cases where the washout effect is acute, stepper/scanner alignment failure occurs resulting in the scrapping of the wafers.
This harsh reality is due to the fact that there is no marker recovery possible, since the epitaxy growth is an extension of the silicon substrate crystal. Another effect is the change in line and space bias. In the case of 8um line and space markers with orientation Silicon, the openings generally increase in size, and in extreme cases merge into one another reducing alignment signal strength to zero. These problems are typically solved by modifying the epitaxy growth rate together with alignment marker optimization. However, there is one effect that is much more difficult to solve – “epitaxy shift”, and this will be the subject of next month’s article.
For more discussion about epitaxy marker “washout “ and other possible solutions, please contact us at
This e-mail address is being protected from spambots. You need JavaScript enabled to view it.