MEMS Metrology Part 2: "Bonded wafer metrology"
MEMS device manufacturers often employ bonded wafers to create mechanical structures such as micro-mirrors for display applications. In this particular example, a completed CMOS wafer is bonded to a Silicon On Insulator (SOI) wafer whose front side has been processed with device circuitry and alignment marks.
The SOI wafer backside is then ground away and the new wafer surface patterned. The successful patterning is dependent on a number of critical factors such as wafer bond quality and front to back alignment accuracy. The ASML system’s 633nm HeNe laser and high gain detection system is capable of capturing an alignment signal from markers buried beneath a thin layer of silicon. Of course, the ASML alignment marker is pre-flipped around the Y access prior to bonding as it is not symmetrical.
This unique alignment capability provides the lithographer with the added benefit of being able to characterize the bonding process. Poor wafer bonding can result in local delamination of the two wafers and bonded wafer distortion. These effects are readily observed when an array of ASML alignment marks is exposed across the surface of the wafer. The aligned position of the mark is compared against the stage grid, and deviations from the nominal position are observed in a modeled vector plot. It is interesting to see the difference between distortion and delamination in the vector plot output. Delamination generates vectors that propagate from a signal point similar to a particle “hot spot”, whereas wafer distortion is more gradual and over a larger area .
These concepts and the actual micro mirror application were presented at Nanotech, May2007 “Novel lithography technique using an ASML stepper/scanner for the manufacture of display devices in MEMS world”
There are numerous other processing techniques that utilize the ASML phase grating alignment method to solve bonded wafer challenges. For more information please contact us at www.simaxlithography.com