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Alignment Marker evaluation

Simax has developed a very straightforward approach to characterization and quantification of the robustness of an alignment marker.

ASML 5500/100 Yield Improvement: Alignment Marker Evaluation

Developing a robust trouble free alignment process has always been an engineering challenge since the invention of automated alignment systems in the 1970’s. The main challenge is fabricating alignment markers that function successfully under a wide range of process variation. Process variations, impacting the automatic alignment systems' ability to consistently detect the alignment markers, include: thin film thickness, etch depth, surface texture, and photoresist coating thickness. Optimization techniques and procedural methodology innovation are what define the photo process engineer’s skills. Simax has developed a very straightforward approach to characterization and quantification of the robustness of an alignment marker. The motto of the process engineering profession is “If you cannot measure it, you cannot improve it.” Simax has developed new techniques for front side and backside alignment using standard ASML test procedures to quantify ASML phase grating alignment markers. The quantification of each alignment marker on a wafer includes three areas: 1. Positioning; 2. Signal strength (with individual detector quantification); and 3. Reproducibility. Innovative alignment marker design optimization is also included in the development of a robust alignment process.

marker evaluation

Diagram Source: HP

The example here shows a large wafer expansion (scaling) error resulting from 2 mis-matched different brand systems.

This e-mail address is being protected from spambots. You need JavaScript enabled to view it. Simax Applications Engineering at simaxlithography.com for assistance in developing a custom alignment mark evaluation program for your process.

Brainerd

 

Steve Brainerd is a Senior Applications Engineer with Simax Lithography. With over 30 years “hands-on” wafer fabrication experience concentrated in semiconductor wafer, MEMs, thick photoresist, solar, and LCD fabrication manufacturing processes, Steve uses his strong analytical skills to develop robust processes for customers. His knowledge and experience include process-equipment startup, process development, process modeling, anti-reflection coating design/modeling, cost reduction, yield improvement, and capacity increases.